The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to reducing power distribution network (PDN) noise in an integrated circuit (e.g., an FPGA).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In high-speed serial interface (HSSI) applications, a high-speed serial input signal (e.g., between approximately 6 to 12 Gbps) to a receiver (RX) of an integrated circuit (IC) device may become attenuated and distorted due to frequency-dependent signal loss across interconnects. One form of distortion that may affect the input signal is intersymbol interference (ISI), which occurs when one data bit of the serial signal interferes with a subsequent data bit. Increases in ISI may produce a measurable degradation of the input signal quality, and the margins of clock and data recovery (CDR) circuitry may be negatively affected.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, according to a designer's design. Additionally, FPGAs may include input/output (I/O) logic, as well as high-speed communication circuitry. For instance, the high-speed communication circuitry may support various communication protocols and may include high-speed transceiver channels through which the FPGA may transmit serial data to and/or receive serial data from circuitry that is external to the FPGA.
ICs, such as an FPGA, are typically designed to be able to operate at a target maximum operating frequency, which is often referred to as “fmax.” Typically, fmax, can be achieved when clean power is supplied to the FPGA. Accordingly, an FPGA may include a power distribution network (PDN) that is tasked with providing such clean power and reference voltages to active devices on the die of the FPGA. However, as technology advances, core voltages of the FPGAs are gradually decreasing, causing an increased sensitivity of the FPGA to PDN fluctuations. Further, as the density of the FPGAs increase, the current draw from the FPGAs also increases, which may result in an increase in the magnitude of PDN fluctuations. For instance, when the current profile of the FPGA design stimulates the PDN RLC network at or close to the resonant frequency of the printed circuit board (PCB) and the device (e.g., die), current variations may cause on-chip voltage to drop, which may negatively affect fmax. Thus, resonant PDN noise that may reduce the operating frequency of FPGAs is becoming increasingly problematic, making it more challenging for FPGAs to achieve their target fmax.